1. Field of the Invention
The present disclosure relates to a flash memory device and an erase method thereof, and more particularly, to a row decoder in a flash memory and an erase method of the flash memory cell using the same.
2. Background of the Related Art
As the degree of integration in the flash memory device is increased, it is required that the thickness of an insulating film having a structure on which an ONO insulating film being a dielectric film between a floating gate and a control gate, i.e., an oxide film, a silicon nitride film and an oxide film are sequentially stacked be reduced. Meanwhile, as more faster erase speed is required, it is also required that an application voltage during an erasing operation be more high.
FIG. 1 illustrates a structure of the flash memory cell.
Referring to FIG. 1, the flash memory cell includes a source region 104 formed in a semiconductor substrate 100, and a drain region 102 formed with a channel region (not shown) intervened between the source region 104 and the drain region 102. A floating gate 108 is formed over the channel region with a tunnel oxide film 106 intervened between them. Further, a control gate 112 is formed over the floating gate 108 with a dielectric film 110 intervened between them. An erasing operation of the flash memory cell is performed by discharging charges (electrons) from the floating gate 108 to the semiconductor substrate 100 by means of F-N (Fowler-Nordheim) tunneling. A common erase method includes applying a negative high voltage (for example, −8V) to the control gate 112 and applying an adequate voltage (for example, +8V) to the semiconductor substrate 100. At this time, the drain region 102 is kept to be high impedance or floated in order to maximize the effect of erasing. A strong electric field is formed between the control gate 112 and the semiconductor substrate 100 by the above method. Due to this, F-N tunneling is generated so that the charges (electrons) within the floating gate 108 are discharged toward the semiconductor substrate 100.
As described above, conventionally, during the erasing operation, the potential difference between the control gate 112 and the semiconductor substrate 100 or source/drain 104/102 becomes about 16V since −8V is applied to the control gate 112 and +8V is applied to the semiconductor substrate 100. This potential difference is distributed by the floating gate 108, so that the voltage applied between the control gate, 112 and the floating gate 108 proportional to the capacitance ratio of the device is about 8V. As the breakdown voltage of the dielectric film 110 between the two gates 112 and 108 becomes 14V, the insulating strength of the ONO insulating film 110 can sufficiently cope with the potential difference organized upon erasing.
As shown in FIG. 2, however, if the floating gate 108 is connected to a contact 1114 (see ‘A’ in FIG. 2), it represents a characteristic of a trans-conductance cell (low Gm Cell) in which current flowing with the voltage of the floating gate 108 and the voltage applied to the drain 102 became equipotential is very low. The yield loss of this cell is improved by a column that was prepared in advance upon designing, i.e., a repair scheme (see FIG. 3) replaced by a redundancy cell. However, as the voltage applied upon erasing is simultaneously applied to a failed cell and a repaired cell, the voltage applied between the control gate 112 and the floating gate 108 thus becomes about 15.5V, as shown in FIG. 2. This is more than the insulating strength of the ONO insulating film and a fail is thus caused during the cycling. In other words, upon erasing, the source 104 and the drain 102 are floated, −8V is applied to the control gate 112 and +8V is applied to the semiconductor substrate 100. At this time, as the semiconductor substrate 100 is a P type and the drain 102 is an N type, a forward bias is applied between the semiconductor substrate 100 and the drain 102, which serves as a P-N diode. Accordingly, the result is that a voltage of about 7.5V is applied to the drain 102 considering voltage drop of the P-N diode. Therefore, when the floating gate 108 is connected to the contact 114, as the voltage of the floating gate 108 and the voltage applied to the drain 102 are the same voltage, the floating gate 108 has a voltage of 7.5V. Also, the result is that a voltage of about 15.5V is applied to the dielectric film 110 between the floating gate 108 and the control gate 112. Due to the above, an insulating break phenomenon may happen.